1. Field of the Invention
The present invention relates to a method of reducing circuit data and a method of simulating circuits. In particular, the present invention relates to a technique of automatically designing an integrated circuit. This technique receives circuit data for an integrated circuit to be simulated, extracts data that influences a result of simulation from the received circuit data, and automatically reduces the circuit data used for the simulation, thereby shortening a simulation time while maintaining the accuracy of simulation.
2. Description of the Related Art
Designing an LSI involves many EDA (electronic design automation) tools in respective stages. These tools are essential for automatically designing ASICs (application specific integrated circuits) such as memories, in particular, SRAMs. The automatic designing technology is improving to meet requirements for large-scale memories and a short turn around time.
FIG. 1 shows the steps of designing an LSI such as a memory. Designing an LSI involves many stages and in each of which the characteristics of a designed circuit must be verified by simulation. The simulation is carried out by, for example, SPICE. The SPICE receives a netlist, which is a text expression of the characteristics and connections of elements of the designed circuit. According to the netlist, the SPICE analyzes and verifies the timing, functions, and power consumption of the elements. The simulation is repeated through the steps shown in FIG. 1. For example, in one of the steps, a schematic data prepared by a circuit drawing editor is used to prepare a netlist for simulation. In another step, data including resistance and capacitance is used to prepare a netlist for simulation. These simulation processes take a large part of time needed for designing an LSI.
Circuit simulators used to design ASICs must secure analytic accuracy, a practical simulation time, a capability of handling large-scale circuits, and a short turn around time.
Prior arts hardly satisfy these requirements for simulating ASICs such as memories, in particular, RAMs. The memories involve a large circuit scale and a variety of word-bit combinations, to take a long simulation time. Fine memories need a precise extraction of parasitic elements, to extend a calculation time for simulation. Large-scale memories have more elements than those (6000 to 7000) being able to be handled by the SPICE, to deteriorate simulation accuracy because the SPICE is able to simulate only part of such large-scale memories. These constitute a bottleneck in designing memory circuits.
To remove the bottleneck, circuit reduction is carried out. The circuit reduction reduces the size of a circuit to be simulated, to thereby shorten a simulation time to a practical level.
To simulate a large-scale ASIC such as a memory, a reduced netlist is prepared for a simulator. The reduced netlist must secure the accuracy of simulation in addition to sufficiently reducing the circuit scale of the memory to simulate.
A reduction method according to a conventional scheme will be explained.
A reduction of a circuit such as a RAM is usually manual according to the conventional scheme. The prior art manually prepares an equivalent circuit of a circuit, and the equivalent circuit is small enough to be simulated by the SPICE. For example, a RAM has regularly arranged parts as shown in FIG. 2(A), and the prior art reduces the regular parts into an equivalent capacitance element of FIG. 2(B).
The conventional scheme carries out this reduction manually, to critically elongate a design period and provide an unsatisfactory reduction result in circuit scale. Since simulation must be repeated to verify the characteristics of a circuit in each design stage, the manual prior art worsens the problem of long design period.
To automate the reduction, Sony Semiconductor Company proposed PASTEL (parameterized memory characterization system). FIG. 3 shows the functional structure and process sequence of the PASTEL.
Reduction by the PASTEL will be explained.
A given SRAM is decomposed into leaf cells serving as units to be repeatedly arranged and connected. Each leaf cell is provided with layout data. According to the layout data of each leaf cell, Arcadia (TM) of Synopsys company, which is a parasitic element extracting program, extracts transistors, parasitic resistors, and parasitic capacitors from each leaf cell. Based on the extracted elements, a SPICE netlist is prepared for each leaf cell.
Separately from this, reduction models are prepared beforehand according to the regularity and design characterization of SRAM cells in case the SRAM cells are loaded. The models are used to carry out pattern matching on the SPICE netlists, thereby providing reduced netlists for the leaf cells, respectively.
A reduction model of memory cells is prepared as shown in FIG. 4. A part shown in FIG. 4(A) is changed into an equivalent circuit of FIG. 4(B). Such equivalent circuits are obtained by multiplying each effective width of transistor by a necessary number of bits.
The reduced netlists prepared for the leaf cells are synthesized into a reduced netlist representing the SRAM as a whole.
The tool of FIG. 3 carries out reduction according to reduced SRAM reduction models, and therefore, is capable of sufficiently reducing the netlist of a given SRAM with an acceptable accuracy. This tool, however, recognizes only given cell patterns, and therefore, is inapplicable to other circuits such as logic circuits. Namely, the tool of FIG. 3 is not versatile and is applicable only to limited circuits.
The tool of FIG. 3 (hereinafter referred to as the first prior art) must have a file of reduction pattern models and is unable to automatically recognize and reduce memory cells from netlists alone.
Since the first prior art employs the pattern matching, one must manually prepare reduction pattern models beforehand and must collate each part of a given circuit with the reduction pattern models. If any part of the given circuit matches with one of the reduction pattern models, the part is replaced with the reduction pattern model.
Manually preparing the reduction pattern models is laborious. The first prior art usually prepares 12 reduction pattern models for memory cells and several tens of reduction pattern models for peripheral control logic parts and must prepare different reduction pattern models for different parameterized memories, i.e., SRAMs and DRAMs for ASICs. These parameterized memories are prepared in different types of architecture for each company.
Namely, the first prior art must prepare many reduction pattern models to design different SRAMs and DRAMs for each type. This is laborious for users. In addition, the pattern matching of the first prior art needs a longer time as the number of patterns increases because the first prior art collates each part of a target circuit with each pattern.
A second prior art is ULTIMA-PR(TM) of Ultima company or STAR-RC(TM) of Avantil company. The second prior art reduces parasitic elements such as parasitic resistors and capacitors of wiring models.
The second prior art reduces only parasitic resistors and capacitors and is unable to reduce transistors. Namely, the second prior art is incapable of providing sufficiently reduced SPICE netlists for large-scale circuits, and therefore, is incapable of simulating large circuits within a practical time.
Netlists prepared by the second prior art are too large to carry out SPICE simulation, need a lot of computer resources, or take a long processing time, e.g., one week or over.
As mentioned above, the prior arts need a long reduction time and are unable to provide netlists sufficiently small for simulators. The prior arts are applicable only to limited circuits and elements, and therefore, are not versatile. When designing large-scale circuits, the prior arts frequently require computer resources exceeding an available hardware quantity, thereby failing simulation.
The present invention has been made to solve the above problems of the prior arts such as a long reduction time, inaccurate reduction, insufficient reduction, and limited application.
An object of the present invention is to provide a method of reducing circuit data to be simulated, by extracting element data that influences a result of simulation out of the circuit data, thereby shortening a simulation time while maintaining the accuracy of simulation.
Still another object of the present invention is to provide a method of reducing circuit data to be simulated only according to the characteristics of MOS transistors, thereby making the method versatile.
Still another object of the present invention is to provide a method of simulating a circuit by extracting element data that influences a result of simulation out of the circuit, preparing a reduced circuit from the extracted data, and using the reduced circuit for simulation, thereby shortening a simulation time while maintaining the accuracy of simulation.
Still another object of the present invention is to provide a computer readable medium for storing a circuit reduction program for extracting element data that influences a result of simulation out of given circuit data and preparing reduced circuit data from the extracted data, thereby shortening a simulation time while maintaining the accuracy of simulation. Also provided is a computer readable medium for storing a simulation program for simulating a given circuit according to the reduction method of the present invention.
To accomplish the objects, the present invention finds a range in which an input signal propagates and this propagation influences an observation point in a given circuit according to the characteristics of MOS transistors and extracts nodes and elements from the range. According to the extracted nodes, the present invention reduces the given circuit. This technique is applicable to a wide variety of integrated circuits.
Elements contained in a circuit to be reduced and simulated are not only MOS transistors but also resistors, capacitors, inductance elements, control power sources, and diodes. Circuit data for a given circuit to be reduced and simulated includes data about elements, nodes, and connections among them.
An example of the reduction method of the present invention is shown in FIG. 5. The method consists of steps S10 to S50. Step S10 receives at least an input vector and/or an observation point for circuit data to simulate. Step S20 sequentially develops the potential state of each node which is in the circuit data and whose potential must be fixed, according to information about fixed-potential nodes and/or initial node values, the information about fixed-potential nodes being obtained from input vectors that activate a route for transmitting an input signal, the initial node values being contained in the circuit data. Step S30 groups nodes according to MOS transistor channels that connect the nodes to one another, and forms an oriented graph from a node group on the gate side of a MOS transistor toward a node group on the channel side of the MOS transistor. Step S40 extracts node groups on a path between an input node at which the state of an input vector varies and an observation node, according to the oriented graphs. Step S50 extracts nodes from the extracted node groups and elements connected to the extracted nodes.
Step S20 may find nodes whose potential is fixed during simulation in the circuit data according to the input vector, and according to the found nodes, determine the ON/OFF state of each MOS transistor whose gate potential is fixed. Step S30 may group nodes according to the ON/OFF states of the MOS transistors. Step S40 may extract nodes from an input signal path between a node group on the gate side of a MOS transistor and a node group on the channel side of the MOS transistor.
This configuration extracts essential data that influences a result of simulation from given circuit data, thereby securing the accuracy of simulation, reducing the size of the circuit to be simulated, and shortening a simulation time.
The simulation method of the present invention simulates the characterization such as timing, functions, consumptive power, and noise of a circuit. This method reduces the circuit to simulate according to the characteristics of MOS transistors contained in the circuit. The method is capable of reducing a variety of circuits including SRAMs, logic circuits, and other circuits.
The method may include the step of deleting at least one of resistors, capacitors, inductance elements, control voltages, and diodes connected to MOS transistors that are not extracted from circuit data. This technique allows not only transistors but also elements such as resistors, capacitors, inductance elements, control voltages, and diodes connected to the transistors to be reduced.
Circuit data handled by the present invention may be circuit data before layout, circuit data after layout, or printed circuit data. The present invention shortens a simulation time in each of circuit designing stages.
Step S10 may optionally specify sub-circuits that must be left in reduced circuit data. This function excludes parts that may cause errors in simulation if reduced or omitted, from parts to be reduced, thereby securing the accuracy of simulation.
Steps S10 and S50 may be carried out on a circuit diagram graphically displayed on a screen. The graphical I/O function enables one to visually enter circuit data, thereby speeding up data input and output operations, reducing input mistakes, and enabling users to visually check reduced circuit parts.
Step S20 may specify the potential state of an arbitrary node in given circuit data and fix the potential states of other nodes according to the specified potential state and input vectors.
Step S40 may control the range of reduction according to the number of stages of load elements entered by user. This technique enables designers to compare and consider simulation accuracy.
Various further and more specific objects, features and advantages of the present invention will appear from the description given below, taken in connection with the accompanying drawings illustrating by way of preferred embodiments of the present invention.